In a dynamic random access memory (DRAM) device, information is stored as a charge on a memory cell capacitor, and this charge may be lost through various paths over time. Accordingly, refresh operations may be needed to recharge the memory cell capacitors to ensure the integrity of the stored data. The interval of time between refresh operations is referred to as the refresh time, and the refresh time can be increased by increasing the capacitance of the memory cell capacitor thus increasing the charge stored by the memory cell capacitor. Alternately, the refresh time can be increased by improving device characteristics so that the leakage of charge from the memory cell capacitor is reduced.
FIG. 1 is a cross-sectional view of a conventional memory device. As shown, device isolation layers 12 on the semiconductor substrate 10 define the cell array region, the core region, and the peripheral circuit region. In the cell array region, a plurality of memory cells are arranged in a matrix, and these memory cells are used to store data. Sense amplifiers and decoders are arranged in the core region to sense the stored data. In the peripheral circuit region, circuits are provided for driving the memory cells of the memory cell array region.
In the cell array region, the transistors include gate electrodes 14 and source/drain regions 16 wherein the source/drain regions 16 comprise doped regions of the substrate having a relatively low dopant concentration. In addition, an insulating layer 18 is formed on the gate electrodes 14 of the cell array region. In the core region and in the peripheral circuit region, transistors include gate electrodes 14 and source/drain regions having either a lightly doped drain (LDD) or double diffused drain (DDD) structure. In particular, source/drain regions of the core and peripheral circuit regions include relatively low dopant concentration regions 16 and relatively high dopant concentration regions 20. In addition, spacers 18a are formed on the sidewalls of the gate electrodes 14 in the core and peripheral circuit regions.
The source/drain regions of the transistors formed in the cell array region have the low dopant concentration regions 16 but do not have high dopant concentration regions. In particular, the low dopant concentration regions 16 of the cell array region can be formed by implanting an N-type dopant such as phosphorous at a dose on the order of 10.sup.13 cm.sup.-2.
Transistors in the core and peripheral circuit regions comprise source/drain regions having the low dopant concentration regions 16 and the high dopant concentration regions 20. The low dopant concentration regions 16 can be formed by implanting an N-type dopant such as phosphorous at a dose of about 10.sup.13 cm.sup.-2. The high dopant concentration regions 20 can be formed by implanting the N-type impurity at a dose on the order of 10.sup.15 cm.sup.-2 after forming the spacers on the sidewalls of the gate electrodes.
As the design rules for memory devices approach 0.2 .mu.m or less, however, the length of the gate electrodes of transistors formed in the core region are reduced as the design rules are reduced. In contrast, the gate electrodes of transistors formed in the peripheral circuit region may be maintained above a certain length to provide a desired current driving ability. Accordingly, length of gate electrodes in the peripheral circuit region may not be reduced in direct proportion to any reductions in the design rules. In a conventional memory device as shown in FIG. 1, a transistor formed in a core region may have a shorter effective channel than a transistor formed in the peripheral circuit region because the gate electrodes formed in the core region may be shorter than those formed in the peripheral circuit region. As shown in FIG. 1, however, the source/drain regions of the core region may be the same as those formed in the peripheral circuit region. Accordingly, reductions in the design rule may result in smaller effective channel lengths in the core region in comparison with those of the peripheral circuit region thereby reducing a punch-through margin of the transistors formed in the core region.
Accordingly, there continues to exist a need in the art for improved methods for forming integrated circuit memory devices and related structures. In particular, methods and structures are needed to provide transistors having reduced leakage current in the cell array region. In addition, transistors in the core region should provide a relatively short gate while maintaining a desired effective channel length to reduce punch-through while providing a desired current driving ability. Furthermore, transistors of the peripheral circuit region should provide an increased current driving ability.